rev. 1.4 may 2002 1/7 this is preliminary information on a new product now in development. details are subject to change without notice. st72260g, st72262g, st72264g 8-bit mcu with flash or rom memory, adc, two 16-bit timers, i 2 c, spi, sci interfaces data briefing n memories 4 k or 8 kbytes program memory: rom or single voltage extended flash (xflash) with read-out protection write protection and in- circuit programming and in-application pro- gramming (icp and iap) 256 bytes ram n clock, reset and supply management enhanced reset system enhanced low voltage supply supervisor (lvd) with 3 programmable levels and auxil- iary voltage detector (avd) with interrupt ca- pability for implementing safe power-down procedures clock sources: crystal/ceramic resonator os- cillators, internal or external rc oscillator, clock security system and bypass for external clock pll for 2x frequency multiplication clock-out capability 4 power saving modes: halt, active halt,wait and slow n interrupt management nested interrupt controller 10 interrupt vectors plus trap and reset 22 external interrupt lines (on 2 vectors) n 22 i/o ports 22 multifunctional bidirectional i/o lines 20 alternate function lines 8 high sink outputs n 3 timers configurable watchdog timer two 16-bit timers with: 2 input captures, 2 out- put compares, external clock input on one tim- er, pwm and pulse generator modes n 3 communications interfaces spi synchronous serial interface i 2 c multimaster interface sci asynchronous serial interface (lin com- patible) n 1 analog peripheral 10-bit adc with 6 input channels n instruction set 8-bit data manipulation 63 basic instructions 17 main addressing modes 8 x 8 unsigned multiply instruction true bit manipulation n development tools full hardware/software development package device summary sdip32 so28 features ST72260G1 st72262g1 st72262g2 st72264g1 program memory - bytes 4k 4k 8k 8k ram (stack) - bytes 256 (128) peripherals watchdog timer, two16-bit timers, spi watchdog timer, two 16-bit timers, spi, adc watchdog timer, two 16-bit timers, spi, adc watchdog timer, two 16-bit timers, spi, sci, i 2 c, adc operating supply 2.4 v to 5.5 v cpu frequency up to 8 mhz (with oscillator up to 16 mhz) pll 4/8 mhz operating temperature -40 c to +85 c packages so28 / sdip32 1
st72260g, st72262g, st72264g 2/7 1 introduction the st72260g, st72262g and st72264g devic- es are members of the st7 microcontroller family. they can be grouped as follows : st72264g devices are designed for mid-range applications with adc, i 2 c and sci interface ca- pabilities. st72262g devices target the same range of ap- plications but without i 2 c interface or sci. st72260g devices are for applications that do not need adc, i 2 c peripherals or sci. all devices are based on a common industry- standard 8-bit core, featuring an enhanced instruc- tion set. the st72f260g, st72f262g, and st72f264g versions feature single-voltage flash memory with byte-by-byte in-circuit programming (icp) capabilities. under software control, all devices can be placed in wait, slow, active-halt or halt mode, re- ducing power consumption when the application is in idle or stand-by state. the enhanced instruction set and addressing modes of the st7 offer both power and flexibility to software developers, enabling the design of highly efficient and compact application code. in addition to standard 8-bit data management, all st7 micro- controllers feature true bit manipulation, 8x8 un- signed multiplication and indirect addressing modes. figure 1. general block diagram 8-bit core alu address and data bus osc1 osc2 reset port b 16-bit timer a port a spi port c 10-bit adc* pb7:0 (8 bits) pc5:0 (6 bits) multi osc internal clock control ram (256 bytes) pa7:0 (8 bits) v ss v dd power supply 16-bit timer b program (4 or 8k bytes) lvd + clock filter sci* memory icd watchdog i 2 c* *not available on some devices, see device summary on page 1.
st72260g, st72262g, st72264g 3/7 2 pin description figure 2. 28-pin so package pinout figure 3. 32-pin sdip package pinout 15 16 17 18 19 20 28 27 26 25 24 23 22 21 1 2 3 4 5 6 7 8 9 10 11 12 13 14 reset osc1 ain3 2 /icap2_b/pc3 ain4 2 /ocmp2_b/pc4 ain5/extclk_a/pc5 icap1_a/pb0 ocmp1_a/pb1 icap2_a/pb2 ocmp2_a/pb3 mosi/pb4 miso/pb5 sck/pb6 ss/pb7 osc2 v dd v ss pc2/mco/ain2 2 pc1/ocmp1_b/ain1 2 pc0/icap1_b/ain0 2 pa7 (hs)/tdo 3 pa6 (hs)/sdai 3 pa5(hs)/rdi 3 pa4 (hs)/scli 3 pa3 (hs) pa2 (hs) pa1 (hs)/iccdata pa0 (hs)/iccclk iccsel ei1 ei0 ei0 or ei1 1 (hs) 20ma high sink capability eix associated external interrupt vector 1 configurable by option byte 2 alternate function not available on st72260 3 alternate function not available on st72260 and st72262 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 29 30 31 32 reset osc1 ain3 2 /icap2_b/pc3 ain4 2 /ocmp2_b/pc4 ain5 2 /extclk_a/pc5 icap1_a/pb0 ocmp1_a/pb1 icap2_a/pb2 ocmp2_a/pb3 mosi/pb4 miso/pb5 sck/pb6 ss/pb7 osc2 nc nc v dd v ss pc2/mco/ain2 2 pc1/ocmp1_b/ain1 2 pc0/icap1_b/ain0 2 pa7 (hs)/tdo 3 pa6 (hsi/sdai 3 pa5 (hs)/rdi 3 pa4 (hs)/scli 3 pa3 (hs) pa2 (hs) pa1 (hs)/iccdata pa0 (hs)/iccclk iccsel nc nc ei1 ei0 ei0 ei1 ei0 or ei1 1 (hs) 20ma high sink capability eix associated external interrupt vector 1 configurable by option byte 2 alternate function not available on st72260 3 alternate function not available on st72260 and st72262
st72260g, st72262g, st72264g 4/7 pin description (cont'd) legend / abbreviations for table 1 : type: i = input, o = output, s = supply input level: a = dedicated analog input in/output level: c t = cmos 0.3 v dd /0.7 v dd with input trigger output level: hs = 20 ma high sink (on n-buffer only) port and control configuration: input: float = floating, wpu = weak pull-up, int = interrupt 1) , ana = analog output: od = open drain 2) , pp = push-pull the reset configuration of each pin is shown in bold. this configuration is valid as long as the device is in reset state. table 1. device pin description pin n pin name type level port / control main function (after reset) alternate function sdip32 so28 input output input output float wpu int ana od pp 1 1 reset i/o c t x x top priority non maskable interrupt (active low) 2 2 osc1 3) i external clock input or resonator oscillator in- verter input or resistor input for rc oscillator 3 3 osc2 3) o resonator oscillator inverter output or capaci- tor input for rc oscillator 4 4 pb7/ss i/o c t x ei1 x x port b7 spi slave select (active low) 5 5 pb6/sck i/o c t x ei1 x x port b6 spi serial clock 6 6 pb5/miso i/o c t x ei1 x x port b5 spi master in/ slave out data 7 7 pb4/mosi i/o c t x ei1 x x port b4 spi master out / slave in data 8nc not connected 9nc 10 8 pb3/ocmp2_a i/o c t x ei1 x x port b3 timer a output compare 2 11 9 pb2/icap2_a i/o c t x ei1 x x port b2 timer a input capture 2 12 10 pb1 /ocmp1_a i/o c t x ei1 x x port b1 timer a output compare 1 13 11 pb0 /icap1_a i/o c t x ei1 x x port b0 timer a input capture 1 14 12 pc5/extclk_a/ain5 i/o c t x ei0/ei1 x x x port c5 timer a input clock or adc analog input 5 15 13 pc4/ocmp2_b/ain4 i/o c t x ei0/ei1 x x x port c4 timer b output compare 2 or adc analog input 4 16 14 pc3/ icap2_b/ain3 i/o c t x ei0/ei1 x x x port c3 timer b input capture 2 or adc analog input 3 17 15 pc2/mco/ain2 i/o c t x ei0/ei1 x x x port c2 main clock output (f cpu )or adc analog input 2 18 16 pc1/ocmp1_b/ain1 i/o c t x ei0/ei1 x x x port c1 timer b output compare 1 or adc analog input 1 19 17 pc0/icap1_b/ain0 i/o c t x ei0/ei1 x x x port c0 timer b input capture 1 or adc analog input 0
st72260g, st72262g, st72264g 5/7 notes : 1. in the interrupt input column, aeixo defines the associated external interrupt vector. if the weak pull-up column (wpu) is merged with the interrupt column (int), then the i/o configuration is a pull-up interrupt in- put, otherwise the configuration is a floating interrupt input. port c is mapped to ei0 or ei1 by option byte. 2. in the open drain output column, ato defines a true open drain i/o (p-buffer and protection diode to v dd are not implemented). 3. osc1 and osc2 pins connect a crystal or ceramic resonator, an external rc, or an external source to the on-chip oscillator. 20 18 pa7/tdo i/o c t hs x ei0 x x port a7 sci output 21 19 pa6/sdai i/o c t hs x ei0 t port a6 i 2 c data 22 20 pa5 /rdi i/o c t hs x ei0 x x port a5 sci input 23 21 pa4/scli i/o c t hs x ei0 t port a4 i 2 c clock 24 nc not connected 25 nc 26 22 pa3 i/o c t hs x ei0 x x port a3 27 23 pa2 i/o c t hs x ei0 x x port a2 28 24 pa1/iccdata i/o c t hs x ei0 x x port a1 in circuit communication data 29 25 pa0/iccclk i/o c t hs x ei0 x x port a0 in circuit communication clock 30 26 iccsel i c t x icc mode pin, must be tied low 31 27 v ss s ground 32 28 v dd s main power supply pin n pin name type level port / control main function (after reset) alternate function sdip32 so28 input output input output float wpu int ana od pp
st72260g, st72262g, st72264g 6/7 3 package characteristics 3.1 package mechanical data figure 4. 32-pin plastic dual in-line package, shrink 400-mil width figure 5. 28-pin plastic small outline package, 300-mil width dim. mm inches min typ max min typ max a 3.56 3.76 5.08 0.140 0.148 0.200 a1 0.51 0.020 a2 3.05 3.56 4.57 0.120 0.140 0.180 b 0.36 0.46 0.58 0.014 0.018 0.023 b1 0.76 1.02 1.40 0.030 0.040 0.055 c 0.20 0.25 0.36 0.008 0.010 0.014 d 27.43 28.45 1.080 1.100 1.120 e 9.91 10.41 11.05 0.390 0.410 0.435 e1 7.62 8.89 9.40 0.300 0.350 0.370 e 1.78 0.070 ea 10.16 0.400 eb 12.70 0.500 ec 1.40 0.055 l 2.54 3.05 3.81 0.100 0.120 0.150 number of pins n 32 d b2 b e a a1 a2 l e1 e ec c ea eb dim. mm inches min typ max min typ max a 2.35 2.65 0.093 0.104 a1 0.10 0.30 0.004 0.012 b 0.33 0.51 0.013 0.020 c 0.23 0.32 0.009 0.013 d 17.70 18.10 0.697 0.713 e 7.40 7.60 0.291 0.299 e 1.27 0.050 h 10.00 10.65 0.394 0.419 h 0.25 0.75 0.010 0.030 a 0 8 0 8 l 0.40 1.27 0.016 0.050 number of pins n 28 hx45 c l a a a1 e b d h e l
st72260g, st72262g, st72264g 7/7 notes: information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in lif e support devices or systems without the express written approval of stmicroelectronics. the st logo is a registered trademark of stmicroelectronics 2002 stmicroelectronics - all rights reserved. purchase of i 2 c components by stmicroelectronics conveys a license under the philips i 2 c patent. rights to use these components in an i 2 c system is granted provided that the system conforms to the i 2 c standard specification as defined by philips. stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. http:/ /www.st.com
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